
`include "defines.v"
//----------------------------------------------------------------
//Module Name : cpu.v
//Description of module:
// 
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/07/22	  
//----------------------------------------------------------------
/* verilator lint_off UNOPTFLAT */
module ysyx_210195_cpu #(
		parameter	AXI_DATA_WIDTH = 64,
		parameter	AXI_ADDR_WIDTH = 64,
		parameter	AXI_ID_WIDTH = 4,
		parameter	AXI_USER_WIDTH = 1
)
(
	input         clock,
    input         reset,

//to slave
	//MASTER write addr
	input	aw_ready_i,			//slave -> master,ready to receive write address
	output	aw_valid_o,			//master -> slave,write address valid
	output	[AXI_ADDR_WIDTH-1:0] aw_addr_o,		//write sddress
	output  [AXI_ID_WIDTH-1:0]	aw_id_o,			//write address channel ID
	output	[AXI_USER_WIDTH-1:0] aw_user_o,		//自定义
	output	[2:0]	aw_prot_o,				//access permissions
	output	[7:0]	aw_len_o,			//burst lenth = aw_len + 1
	output	[2:0]	aw_size_o,			//本次burst中，一次transferde的字节数
	output	[1:0]	aw_burst_o,			//burst_type
	output			aw_lock_o,
	output	[3:0]	aw_cache_o,			//memory types
	output	[3:0]	aw_qos_o,			//Quality of service identifier for a write transaction
	output	[3:0]	aw_region_o,		//多接口时用
	
	//master write data
	input	w_ready_i,
	output	w_valid_o,
	output	[AXI_DATA_WIDTH-1:0]	w_data_o,
	output	[7:0]	w_strb_o,				//标志有效位
	output	w_last_o,						//标志最后一次传输
	output	[AXI_USER_WIDTH-1:0]	w_user_o,
	
	//write response
	output	b_ready_o,
	input	b_valid_i,
	input	[1:0]	b_resp_i,
	input	[AXI_ID_WIDTH-1:0]	b_id_i,
	input	[AXI_USER_WIDTH-1:0]	b_user_i,
	
	//read address channel
	input	ar_ready_i,
	output	ar_valid_o,
	output	[AXI_ADDR_WIDTH-1:0]	ar_addr_o,
	output	[2:0]	ar_prot_o,
	output	[AXI_ID_WIDTH-1:0]	ar_id_o,			//read address channel identifier
	output	[AXI_USER_WIDTH-1:0]	ar_user_o,
	output	[7:0]	ar_len_o,
	output	[2:0]	ar_size_o,
	output	[1:0]	ar_burst_o,
	output		ar_lock_o,
	output	[3:0]	ar_cache_o,
	output	[3:0]	ar_qos_o,
	output	[3:0]	ar_region_o,
	
	//read data channel
	output	r_ready_o,
	input	r_valid_i,
	input	[1:0]	r_resp_i,
	input	[AXI_DATA_WIDTH-1:0]	r_data_i,
	input	r_last_i,
	input	[AXI_ID_WIDTH-1:0]	r_id_i,
	input	[AXI_USER_WIDTH-1:0]	r_user_i,
	
	
	//clint
	output	load_clint_en,
	output	clint_w_ena,
	output	[63:0]	load_store_addr,
	output	[63:0]	store_clint_data,
	output	load_clint_en_exe,
	output	[63:0]	load_clint_addr_exe,
	
	input	time_overstep,
	input	[63:0]	load_clint_data_exe
//	input	[`REG_DATA_LEN-1:0] load_clint_data

);

wire [63:0]	i_if_pc_out;
wire [31:0] i_if_inst;
//wire [`REG_DATA_LEN-1:0] mem_ld_data;
//wire [`INST_ADDR_LEN-1:0] pc_out;
//wire i_if_inst_ena;
//wire load_mem_en;
//wire store_mem_en;
//wire [63:0] store_mask;
wire [63:0] i_exe_data;
wire [63:0] i_id_op2;
wire [63:0]	jump_addr;
wire	pc_sel;									//control MODULE output,control the pc choose
//wire	[`INST_ADDR_LEN-1:0] pc_add;			//result of pc+4
wire	i_if_fetched;
wire	if_valid;
wire	if_ready;
wire	if_req;
wire	[63:0]	inst_data_read;
wire	[63:0]	i_if_addr;
wire	[1:0]	if_size;
wire	[1:0]	if_resp;

wire	[63:0]	mtvec_r;
wire	[63:0]	mepc_r;
//wire	ecall_en;
//wire	mret_en;

wire	if_addr_ctrl;
wire	MTIP;			//csr_reg -> if_stage
wire	time_intr_r;
wire	handshake_done;
wire	i_ctrlid_ecall_en;
wire	i_ctrlid_mret_en;
ysyx_210195_if_stage	ysyx_210195_IF(
	.clk(clock),
	.rst(reset),							//high work
	.exe_data(jump_addr),	//use when jalr,branch
	
	.ecall_en(i_ctrlid_ecall_en),								
	.mret_en(i_ctrlid_mret_en),
	.mtvec(mtvec_r),
	.mepc(mepc_r),
	
//	.MTIP(MTIP),
	.time_intr_r(time_intr_r),			//中断响应
	
	.if_addr_ctrl(if_addr_ctrl),
	
	.pc_sel(pc_sel),
	.if_addr(i_if_addr),
	.pc_out(i_if_pc_out),		//指令寄存器地址
//	.pc_add(pc_add),
//	.inst_ena(i_if_inst_ena),
	.inst(i_if_inst),

	.if_valid(if_valid),
	.if_ready(if_ready),
	.inst_data_read(inst_data_read),
	.if_size(if_size),
	.if_resp(if_resp),
	.if_req(if_req),
	.handshake_done(handshake_done),
	
	.fetched(i_if_fetched)	
		);
wire	id_load_axi_en;
wire	exe_load_axi_en;
wire	ifid_ena;
wire	ifid_rst;
wire	idex_rst;
wire	exmem_rst;
wire	memwb_rst;
		
ysyx_210195_adven_ctrl	ysyx_210195_ADVEN(
	.id_load_axi_en(id_load_axi_en),
	.exe_load_axi_en(exe_load_axi_en),
	.pc_sel(pc_sel),
	.time_intr_r(time_intr_r),
	
	.ifid_ena(ifid_ena),
	.ifid_rst(ifid_rst),
//	output	exmem_ena,
//	output	exmem_rst,
	.idex_rst(idex_rst),
	.exmem_rst(exmem_rst),
	.memwb_rst(memwb_rst),
	.if_addr_ctrl(if_addr_ctrl)

);

ysyx_210195_intr_pro	ysyx_210195_INTR(
	.clk(clock),
	.reset(reset),
	.if_fetched(i_if_fetched),
	.if_addr_ctrl(if_addr_ctrl),
	.MTIP(MTIP),
	.time_intr_r(time_intr_r)
);

//wire	o_if_time_intr_r;
//wire	o_if_inst_ena;
wire	[`INST_LEN-1:0] o_if_inst;
wire	[`INST_ADDR_LEN-1:0] o_if_pc_out;
//wire	o_if_fetched;
//wire	[`INST_ADDR_LEN-1:0] o_if_addr;
//wire	ifid_rst_i;
//assign	ifid_rst_i = ifid_rst | reset;
ysyx_210195_IFID_reg	ysyx_210195_IFID(
	.clk(clock),
	.reset(reset),
	.ifid_rst(ifid_rst),
	.handshake_done(i_if_fetched),
	.ifid_ena(ifid_ena),
	
//	.i_if_time_intr_r(i_if_time_intr_r),
//	.i_if_inst_ena(i_if_inst_ena),
	.i_if_inst(i_if_inst),
	.i_if_pc_out(i_if_pc_out),
//	.i_if_fetched(i_if_fetched),
//	.i_if_addr(i_if_addr),
	
//	.o_if_time_intr_r(o_if_time_intr_r),
//	.o_if_inst_ena(o_if_inst_ena),
	.o_if_inst(o_if_inst),
	.o_if_pc_out(o_if_pc_out)
//	.o_if_fetched(o_if_fetched)
//	.o_if_addr(o_if_addr)
	
	);

wire	[`REG_DATA_LEN-1:0]	rs1_data;				//output data from reg to id_stage	
wire	[`REG_DATA_LEN-1:0]	rs2_data;	
wire	i_id_rs1_r_ena;					//output of id to reg
wire	i_id_rs2_r_ena;
wire	[4:0]	i_id_rs1_r_addr;
wire	[4:0]	i_id_rs2_r_addr;
wire	i_id_rd_w_ena;
wire	[4:0]	i_id_rd_w_addr;
//wire	[5:0]	i_id_inst_type;
wire	[7:0]	i_id_inst_opcode;
wire	[`REG_DATA_LEN-1:0]	i_id_op1;		//operation 1
//wire	[`REG_DATA_LEN-1:0]	op2;
wire	[`REG_DATA_LEN-1:0] i_id_extend_imm;
wire	[6:0]	i_id_funct7;
wire	i_id_csr_imm_ena;
wire	[`REG_DATA_LEN-1:0]	i_id_csr_imm;
ysyx_210195_id_stage	ysyx_210195_ID(
	.rst(reset),
	.inst(o_if_inst),					//32 bit inst code
	.rs1_data(rs1_data),			//op1 in rs1////////////////////////////////////////////////////
	.rs2_data(rs2_data),			//op2 in rs2//////////////////////////////////////////////////////
  
  
	.rs1_r_ena(i_id_rs1_r_ena),					//rs1 read enable
	.rs1_r_addr(i_id_rs1_r_addr),			//rs1 read addr
	.rs2_r_ena(i_id_rs2_r_ena),					//rs2 read enable
	.rs2_r_addr(i_id_rs2_r_addr),			//rs2 read addr
	.rd_w_ena(i_id_rd_w_ena),					//rd write enable
	.rd_w_addr(i_id_rd_w_addr),			//rd write addr
	
	.csr_imm_ena(i_id_csr_imm_ena),
	.csr_imm(i_id_csr_imm),
  
//	.inst_type(i_id_inst_type),			//6 inst type--one hot code			
	.inst_opcode(i_id_inst_opcode),		//自定义8位操作码，{func3[2:0],opcode[6:2]}
	.op1(i_id_op1),			//64bit op1 data
	.op2(i_id_op2),				//64bit op2 data
	.extend_imm(i_id_extend_imm),				//立即数符号扩展
	.funct7(i_id_funct7)
);

wire	branch_eq;
wire	branch_ne;
wire	branch_lt;
wire	branch_ge;
wire	branch_ltu;
wire	branch_geu;

//wire	jalr_en;
//wire	jal_en;
wire	branch_en;
wire	[63:0]	conflict_op1;
wire	[63:0]	conflict_op2;
ysyx_210195_branch_comp	ysyx_210195_BRANCH(
	.branch_en(branch_en),							//分支比较使能
	.op1(conflict_op1),			
	.op2(conflict_op2),
	.eq(branch_eq),				//equal
	.ne(branch_ne),				//not equal
	.lt(branch_lt),				//less than
	.ge(branch_ge),				//greater than or equal
	.ltu(branch_ltu),			//无符号，less than
	.geu(branch_geu)				//无符号，greater than or equal
	);
wire	[1:0]	i_ctrlid_wb_sel;

//wire	ifif_fetched;

wire	id_load_mem_en;
		
//wire	id_load_axi_en;
//wire	id_load_clint_en;
//wire	id_store_axi_en;
//wire 	id_store_clint_en;
//wire	id_store_mem_en;
	
ysyx_210195_cpu_ctrl_id	ysyx_210195_CTRL_ID(
//		.clock(clock),
		.inst_opcode(i_id_inst_opcode),
		.branch_eq(branch_eq),
		.branch_ne(branch_ne),
		.branch_lt(branch_lt),
		.branch_ge(branch_ge),
		.branch_ltu(branch_ltu),
		.branch_geu(branch_geu),
//		input	[63:0] ram_addr,
		.time_intr_r(time_intr_r),			//中断响应
//		input	[63:0] load_store_addr,			//exe_data
		
		.funct7(i_id_funct7),
		.inst(o_if_inst),
		
//		input	if_fetched,	

//		.jalr_en(jalr_en),
//		.jal_en(jal_en),		
		.wb_sel(i_ctrlid_wb_sel),
		.pc_sel(pc_sel),
		.branch_en(branch_en),
		.ecall_en(i_ctrlid_ecall_en),
		.mret_en(i_ctrlid_mret_en),
		
		.op1(conflict_op1),
		.op2(conflict_op2),
		.extend_imm(i_id_extend_imm),
//		.if_fetched(i_if_fetched),
		.pc_out(o_if_pc_out),
		.jump_addr(jump_addr),
		.load_mem_en(id_load_mem_en),
		
		.load_axi_en(id_load_axi_en)
//		.load_clint_en(id_load_clint_en),
//		.store_axi_en(id_store_axi_en),
//		.store_clint_en(id_store_clint_en),
//		.store_mem_en(id_store_mem_en)

);
wire	o_id_rd_w_ena;
wire	[4:0]	o_id_rd_w_addr;
wire	[1:0]	o_ctrlid_wb_sel;
wire	[`INST_ADDR_LEN-1:0] o_ifif_pc_out;
wire	i_ctrlexe_load_clint_en;
wire	i_csrunit_csr_r_ena;
wire	[`INST_ADDR_LEN-1:0]	o_ififif_pc_out;
wire	o_idid_rd_w_ena;				//--csr_reg,regfile
wire	[4:0]	o_idid_rd_w_addr;		//--csr_reg,regfile
wire	[1:0]	o_ctrlidctrlid_wb_sel;
wire	[`REG_DATA_LEN-1:0]	o_exe_data;
wire	o_csrunit_csr_r_ena;
wire	[63:0]	o_csrunit_csr_r_data;
wire	o_ctrlexe_load_clint_en;
wire	[63:0]	o_clint_load_data;

wire	[`INST_ADDR_LEN-1:0]	o_ifififif_pc_out;
wire	o_ididid_rd_w_ena;				//--csr_reg,regfile
wire	[4:0]	o_ididid_rd_w_addr;		//--csr_reg,regfile
wire	[1:0]	o_ctrlidctrlidctrlid_wb_sel;			//regfile
wire	[`REG_DATA_LEN-1:0]	o_exeexe_data;		//--WB
wire	o_csrunitcsrunit_csr_r_ena;			//wb
wire	[63:0]	o_csrunitcsrunit_csr_r_data;
wire	o_ctrlexectrlexe_load_clint_en;		//regfile
wire	[63:0]	o_lspro_axi_ld_data;
wire	[63:0]	o_clintclint_load_data;
wire	[`REG_DATA_LEN-1:0]	csr_r_data_unit;
ysyx_210195_data_conf	ysyx_210195_CONFLICT(
//本级
	.i_id_rs1_r_ena(i_id_rs1_r_ena),				//本级rs1_ena源操作数1
	.i_id_rs1_r_addr(i_id_rs1_r_addr),	//本级rs1_addr源操作数1
	.i_id_op1(i_id_op1),
	.i_id_rs2_r_ena(i_id_rs2_r_ena),				//本级rs2_ena源操作数2
	.i_id_rs2_r_addr(i_id_rs2_r_addr),	//本级rs2_addr源操作数2
	.i_id_op2(i_id_op2),
//上一级
	.o_id_rd_w_ena(o_id_rd_w_ena),				//上一级rd_ena
	.o_id_rd_w_addr(o_id_rd_w_addr),		//上一级rd_w_addr
	.i_exe_data(i_exe_data),			//上一级执行结果
	.o_ctrlid_wb_sel(o_ctrlid_wb_sel),	//上一级wb_sel
	.o_ifif_pc_out(o_ifif_pc_out),		//上一级pc_out
	.i_csrunit_csr_r_ena(i_csrunit_csr_r_ena),
	.csr_r_data_unit(csr_r_data_unit),
	.i_ctrlexe_load_clint_en(i_ctrlexe_load_clint_en),
	.load_clint_data_exe(load_clint_data_exe),

//上两级
	.o_idid_rd_w_ena(o_idid_rd_w_ena),			//上两级rd_w_ena
	.o_idid_rd_w_addr(o_idid_rd_w_addr),	//上两级rd_w_addr
	.i_exeexe_data(o_exe_data),		//上两级执行结果
	.o_ctrlidctrlid_wb_sel(o_ctrlidctrlid_wb_sel),	//上两级wb_sel
	.o_ififif_pc_out(o_ififif_pc_out),		//上两级pc_out
	.o_csrunit_csr_r_ena(o_csrunit_csr_r_ena),
	.o_csrunit_csr_r_data(o_csrunit_csr_r_data),
	.o_ctrlexe_load_clint_en(o_ctrlexe_load_clint_en),
	.o_clint_load_data(o_clint_load_data),
	
//上三级
	.o_ididid_rd_w_ena(o_ididid_rd_w_ena),			//上三级rd_w_ena
	.o_ididid_rd_w_addr(o_ididid_rd_w_addr),
	.o_exeexe_data(o_exeexe_data),
	.o_ctrlidctrlidctrlid_wb_sel(o_ctrlidctrlidctrlid_wb_sel),
	.o_ifififif_pc_out(o_ifififif_pc_out),
	.o_lspro_axi_ld_data(o_lspro_axi_ld_data),
	.o_csrunitcsrunit_csr_r_ena(o_csrunitcsrunit_csr_r_ena),
	.o_csrunitcsrunit_csr_r_data(o_csrunitcsrunit_csr_r_data),
	.o_ctrlexectrlexe_load_clint_en(o_ctrlexectrlexe_load_clint_en),
	.o_clintclint_load_data(o_clintclint_load_data),
	
//输出判断后的源操作数
	.conflict_op1(conflict_op1),
	.conflict_op2(conflict_op2)
);

wire	o_id_rs1_r_ena;
wire	[4:0]	o_id_rs1_r_addr;
//wire	o_id_rs2_r_ena;
//wire	[4:0]	o_id_rs2_r_addr;

wire	o_id_csr_imm_ena;
wire	[`REG_DATA_LEN-1:0]	o_id_csr_imm;
//wire	[5:0]	o_id_inst_type;
wire	[7:0]	o_id_inst_opcode;
wire	[`REG_DATA_LEN-1:0]	o_id_op1;
wire	[`REG_DATA_LEN-1:0]	o_id_op2;
wire	[`REG_DATA_LEN-1:0]	o_id_extend_imm;
wire	[6:0]	o_id_funct7;


wire	o_ctrlid_ecall_en;
wire	o_ctrlid_mret_en;
	
//wire	o_ifif_fetched;
//wire	o_ifif_time_intr_r;

//wire 	[`INST_ADDR_LEN-1:0] o_ifif_addr;
wire 	o_ctrlid_load_mem_en;
//wire	idex_rst_i;
//assign	idex_rst_i = reset | idex_rst;
ysyx_210195_IDEX_reg	ysyx_210195_IDEX_REG(
	.clk(clock),
	.reset(reset),
	.handshake_done(i_if_fetched),
	.idex_rst(idex_rst),
	.idex_ena(1'b1),
	
	.i_id_rs1_r_ena(i_id_rs1_r_ena),
	.i_id_rs1_r_addr(i_id_rs1_r_addr),
//	.i_id_rs2_r_ena(i_id_rs2_r_ena),
//	.i_id_rs2_r_addr(i_id_rs2_r_addr),
	.i_id_rd_w_ena(i_id_rd_w_ena),
	.i_id_rd_w_addr(i_id_rd_w_addr),
	.i_id_csr_imm_ena(i_id_csr_imm_ena),
	.i_id_csr_imm(i_id_csr_imm),
//	.i_id_inst_type(i_id_inst_type),
	.i_id_inst_opcode(i_id_inst_opcode),
	.i_id_op1(conflict_op1),
	.i_id_op2(conflict_op2),
	.i_id_extend_imm(i_id_extend_imm),
	.i_id_funct7(i_id_funct7),
//from ctrlid	
	.i_ctrlid_wb_sel(i_ctrlid_wb_sel),			//regfile
	.i_ctrlid_ecall_en(i_ctrlid_ecall_en),
	.i_ctrlid_mret_en(i_ctrlid_mret_en),
	.i_ctrlid_load_mem_en(id_load_mem_en),
//from	if	
//	.i_ifif_fetched(o_if_fetched),
//	.i_ifif_time_intr_r(o_if_time_intr_r),
	.i_ifif_pc_out(o_if_pc_out),
//	.i_ifif_addr(o_if_addr),
	
	.o_id_rs1_r_ena(o_id_rs1_r_ena),
	.o_id_rs1_r_addr(o_id_rs1_r_addr),
//	.o_id_rs2_r_ena(o_id_rs2_r_ena),
//	.o_id_rs2_r_addr(o_id_rs2_r_addr),
	.o_id_rd_w_ena(o_id_rd_w_ena),
	.o_id_rd_w_addr(o_id_rd_w_addr),
	.o_id_csr_imm_ena(o_id_csr_imm_ena),
	.o_id_csr_imm(o_id_csr_imm),
//	.o_id_inst_type(o_id_inst_type),
	.o_id_inst_opcode(o_id_inst_opcode),
	.o_id_op1(o_id_op1),
	.o_id_op2(o_id_op2),
	.o_id_extend_imm(o_id_extend_imm),
	.o_id_funct7(o_id_funct7),
	
	.o_ctrlid_wb_sel(o_ctrlid_wb_sel),
	.o_ctrlid_ecall_en(o_ctrlid_ecall_en),
	.o_ctrlid_mret_en(o_ctrlid_mret_en),
	.o_ctrlid_load_mem_en(o_ctrlid_load_mem_en),
	
//	.o_ifif_fetched(o_ifif_fetched),
//	.o_ifif_time_intr_r(o_ifif_time_intr_r),
	.o_ifif_pc_out(o_ifif_pc_out)
//	.o_ifif_addr(o_ifif_addr)
);


/*
wire	branch_eq;
wire	branch_ne;
wire	branch_lt;
wire	branch_ge;
wire	branch_ltu;
wire	branch_geu;

//wire	load_mem_en;
wire	jalr_en;
wire	jal_en;
wire	[1:0] wb_sel;
//wire	store_mem_en;
wire	branch_en;
//wire	mret_en;
wire	load_axi_en;
wire	store_axi_en;
wire	store_clint_en;
cpu_ctrl	CTRL(
		.inst_opcode(inst_opcode),
		.branch_eq(branch_eq),
		.branch_ne(branch_ne),
		.branch_lt(branch_lt),
		.branch_ge(branch_ge),
		.branch_ltu(branch_ltu),
		.branch_geu(branch_geu),
		.ram_addr(exe_data),
		.time_intr_r(time_intr_r),
		.load_store_addr(exe_data),
		
		.funct7(funct7),
		.if_fetched(fetched),
		.load_mem_en(load_mem_en),
		
		.load_axi_en(load_axi_en),
		.load_clint_en(load_clint_en),
		.store_axi_en(store_axi_en),
		.store_clint_en(store_clint_en),		
		
		
		.jalr_en(jalr_en),
		.jal_en(jal_en),
		.wb_sel(wb_sel),
		.pc_sel(pc_sel),
		.store_mem_en(store_mem_en),
		.branch_en(branch_en),
		.store_mask(store_mask),
		.ecall_en(ecall_en),
		.mret_en(mret_en)
//		.pc_from_mepc(pc_from_mepc)
		);
*/
//assign	clint_w_ena = store_clint_en & fetched & (~time_intr_r);
//wire	[5:0] inst_type_o;
//wire	[`REG_DATA_LEN-1:0] exe_data	

wire	[`REG_DATA_LEN-1:0]	csr_r_data;	
ysyx_210195_exe_stage	ysyx_210195_EXE(
  .rst(reset),
//  .inst_type_i(o_id_inst_type),
  .inst_opcode(o_id_inst_opcode),
  .op1(o_id_op1),
  .op2(o_id_op2),
  .extend_imm(o_id_extend_imm),
  .funct7(o_id_funct7),
  .pc(o_ifif_pc_out),
  .csr_r_data(csr_r_data),
  
//  .inst_type_o(inst_type_o),
  .exe_data(i_exe_data)
);
//wire	load_mem_en;
//wire	store_mem_en;
wire	i_ctrlexe_load_axi_en;

wire	i_ctrlexe_store_axi_en;
wire	i_ctrlexe_store_clint_en;
ysyx_210195_cpu_ctrl_exe	ysyx_210195_CTRL_EXE(
		.inst_opcode(o_id_inst_opcode),
//		input	branch_eq,
//		input	branch_ne,
//		input	branch_lt,
//		input	branch_ge,
//		input	branch_ltu,
//		input	branch_geu,
//		.ram_addr(i_exe_data),
//		input	time_intr_r,			//中断响应
		.load_store_addr(i_exe_data),			//exe_data
		
//		input	[6:0]	funct7,
		
//		.if_fetched(o_ifif_fetched),	
		
		.load_mem_en(o_ctrlid_load_mem_en),
		
		.load_axi_en(i_ctrlexe_load_axi_en),
		.load_clint_en(i_ctrlexe_load_clint_en),
		.store_axi_en(i_ctrlexe_store_axi_en),
		.store_clint_en(i_ctrlexe_store_clint_en)
//		.store_mem_en(store_mem_en)
//		output	[1:0] wb_sel
//		output	reg [63:0] store_mask
);
assign  exe_load_axi_en = i_ctrlexe_load_axi_en;
wire	[11:0]	i_csrunit_csr_addr;
wire	i_csrunit_csr_w_ena;
wire	[`REG_DATA_LEN-1:0]	i_csrunit_csr_w_data;




ysyx_210195_csr_unit	ysyx_210195_CSR_UNIT(
		.inst_opcode(o_id_inst_opcode),
		.extend_imm(o_id_extend_imm),				//其中包含了CSR地址
		.rs1_r_ena(o_id_rs1_r_ena),
		.rs1_r_addr(o_id_rs1_r_addr),
		.op1(o_id_op1),
		.rd_w_ena(o_id_rd_w_ena),
		.rd_w_addr(o_id_rd_w_addr),
		.csr_r_data(csr_r_data_unit),
		.csr_imm_ena(o_id_csr_imm_ena),							//csr立即数使能
		.csr_imm(o_id_csr_imm),						//csr立即数
		
		.csr_addr(i_csrunit_csr_addr),
		.csr_w_ena(i_csrunit_csr_w_ena),
		.csr_w_data(i_csrunit_csr_w_data),
		.csr_r_ena(i_csrunit_csr_r_ena)
		);
		
assign	load_clint_en_exe = i_ctrlexe_load_clint_en;
assign	load_clint_addr_exe = i_exe_data;



//wire	o_ififif_fetched;
//wire	o_ififif_time_intr_r;
//wire	[`INST_ADDR_LEN-1:0] o_ififif_addr;
	
//wire	o_idid_rs1_r_ena;				//--csr_reg,regfile
//wire	[4:0]	o_idid_rs1_r_addr;	//--csr_reg,regfile
//wire	o_idid_rs2_r_ena;				//--regfile
//wire	[4:0]	o_idid_rs2_r_addr;	//--regfile

wire	[`REG_DATA_LEN-1:0] o_idid_op2;	
wire	[7:0]	o_idid_inst_opcode;
	

wire	o_ctrlidctrlid_ecall_en;
wire	o_ctrlidctrlid_mret_en;
	

	
wire	[11:0]	o_csrunit_csr_addr;
wire	o_csrunit_csr_w_ena;
wire	[`REG_DATA_LEN-1:0]	o_csrunit_csr_w_data;

	
wire	o_ctrlexe_load_axi_en;

wire	o_ctrlexe_store_axi_en;
wire	o_ctrlexe_store_clint_en;
//wire	exmem_rst_i;
//assign	exmem_rst_i = exmem_rst | reset;


ysyx_210195_EXMEM_reg	ysyx_210195_EXMEM_REG(
	.clk(clock),
	.reset(reset),
	.handshake_done(i_if_fetched),
	.exmem_rst(exmem_rst),
	.exmem_ena(1'b1),
//from if
	.i_ififif_pc_out(o_ifif_pc_out),		//regfile
//	.i_ififif_fetched(o_ifif_fetched),								//regfile
//	.i_ififif_time_intr_r(o_ifif_time_intr_r),					//wb
//	.i_ififif_addr(o_ifif_addr),
	
//from id
//	.i_idid_rs1_r_ena(o_id_rs1_r_ena),				//--csr_reg,regfile
//	.i_idid_rs1_r_addr(o_id_rs1_r_addr),	//--csr_reg,regfile
//	.i_idid_rs2_r_ena(o_id_rs2_r_ena),				//--regfile
//	.i_idid_rs2_r_addr(o_id_rs2_r_addr),	//--regfile
	.i_idid_rd_w_ena(o_id_rd_w_ena),				//--csr_reg,regfile
	.i_idid_rd_w_addr(o_id_rd_w_addr),		//--csr_reg,regfile
	.i_idid_op2(o_id_op2),	
	.i_idid_inst_opcode(o_id_inst_opcode),
//from	ctrlid
	.i_ctrlidctrlid_wb_sel(o_ctrlid_wb_sel),			//regfile
	.i_ctrlidctrlid_ecall_en(o_ctrlid_ecall_en),					//wb
	.i_ctrlidctrlid_mret_en(o_ctrlid_mret_en),					//wb

//from exe
	.i_exe_data(i_exe_data),		//--WB
//from CSR_UNIT
	.i_csrunit_csr_addr(i_csrunit_csr_addr),		//wb
	.i_csrunit_csr_w_ena(i_csrunit_csr_w_ena),			//wb
	.i_csrunit_csr_w_data(i_csrunit_csr_w_data),		//wb
	.i_csrunit_csr_r_ena(i_csrunit_csr_r_ena),			//wb
	.i_csrunit_csr_r_data(csr_r_data_unit),
//from ctrlexe
	.i_ctrlexe_load_axi_en(i_ctrlexe_load_axi_en),			//regfile
	.i_ctrlexe_load_clint_en(i_ctrlexe_load_clint_en),		//regfile
	.i_ctrlexe_store_axi_en(i_ctrlexe_store_axi_en),		//regfile	
	.i_ctrlexe_store_clint_en(i_ctrlexe_store_clint_en),		//regfile

//	input	i_ctrlexe_wb_sel,				//regfile

	.i_clint_load_data(load_clint_data_exe),
	
	.o_ififif_pc_out(o_ififif_pc_out),
//	.o_ififif_fetched(o_ififif_fetched),
//	.o_ififif_time_intr_r(o_ififif_time_intr_r),
//	.o_ififif_addr(o_ififif_addr),
	
//	.o_idid_rs1_r_ena(o_idid_rs1_r_ena),				//--csr_reg,regfile
//	.o_idid_rs1_r_addr(o_idid_rs1_r_addr),	//--csr_reg,regfile
//	.o_idid_rs2_r_ena(o_idid_rs2_r_ena),				//--regfile
//	.o_idid_rs2_r_addr(o_idid_rs2_r_addr),	//--regfile
	.o_idid_rd_w_ena(o_idid_rd_w_ena),				//--csr_reg,regfile
	.o_idid_rd_w_addr(o_idid_rd_w_addr),		//--csr_reg,regfile
	.o_idid_op2(o_idid_op2),
	.o_idid_inst_opcode(o_idid_inst_opcode),	
	
	.o_ctrlidctrlid_wb_sel(o_ctrlidctrlid_wb_sel),
	.o_ctrlidctrlid_ecall_en(o_ctrlidctrlid_ecall_en),
	.o_ctrlidctrlid_mret_en(o_ctrlidctrlid_mret_en),
	
	.o_exe_data(o_exe_data),
	
	.o_csrunit_csr_addr(o_csrunit_csr_addr),
	.o_csrunit_csr_w_ena(o_csrunit_csr_w_ena),
	.o_csrunit_csr_w_data(o_csrunit_csr_w_data),
	.o_csrunit_csr_r_ena(o_csrunit_csr_r_ena),
	.o_csrunit_csr_r_data(o_csrunit_csr_r_data),
	
	.o_ctrlexe_load_axi_en(o_ctrlexe_load_axi_en),
	.o_ctrlexe_load_clint_en(o_ctrlexe_load_clint_en),
	.o_ctrlexe_store_axi_en(o_ctrlexe_store_axi_en),
	.o_ctrlexe_store_clint_en(o_ctrlexe_store_clint_en),
//	output	reg o_ctrlexe_wb_sel
	.o_clint_load_data(o_clint_load_data)
	
);

wire	ls_ready_i;
wire	[63:0]	load_data_i;
wire	[1:0]	ls_resp;
wire	ls_valid_o;
wire	ls_req_o;
wire	[1:0]	ls_size_o;
wire	[`REG_DATA_LEN-1:0]	i_lspro_axi_ld_data;		//load_axi_data
//wire	i_lspro_fetched;		//load_fetched
ysyx_210195_ls_pro	ysyx_210195_LS_PRO(
//from axi_arbi	
	.clk(clock),
	.reset(reset),
	.ls_ready_i(ls_ready_i),
	.load_data_i(load_data_i),	
	.ls_resp(ls_resp),
	
	.if_fetched(i_if_fetched),
	
	.load_axi_en(o_ctrlexe_load_axi_en),
	.store_axi_en(o_ctrlexe_store_axi_en),
	.inst_opcode(o_idid_inst_opcode),
	
//to arbi	
	.ls_valid_o(ls_valid_o),
	.ls_req_o(ls_req_o),
//	output 	[63:0]	ls_addr_o,
//	output	[63:0]	store_data_o,
	.ls_size_o(ls_size_o),
//to reg
	.mem_ld_data(i_lspro_axi_ld_data)			//->reg
//	.load_fetched(i_lspro_fetched)	
	);
	

//wire	o_ifififif_fetched;
//wire	o_ifififif_time_intr_r;
//wire	[`INST_ADDR_LEN-1:0]	o_ifififif_addr;

//wire	o_ididid_rs1_r_ena;				//--csr_reg,regfile
//wire	[4:0]	o_ididid_rs1_r_addr;	//--csr_reg,regfile
//wire	o_ididid_rs2_r_ena;				//--regfile
//wire	[4:0]	o_ididid_rs2_r_addr;	//--regfile
wire	[`REG_DATA_LEN-1:0] o_ididid_op2;	
wire	o_ctrlidctrlidctrlid_ecall_en;					//wb
wire	o_ctrlidctrlidctrlid_mret_en;					//wb
	
	
wire	[11:0]	o_csrunitcsrunit_csr_addr;		//wb
wire	o_csrunitcsrunit_csr_w_ena;			//wb
wire	[`REG_DATA_LEN-1:0]	o_csrunitcsrunit_csr_w_data;		//wb
	
wire	o_ctrlexectrlexe_load_axi_en;			//regfile

wire	o_ctrlexectrlexe_store_clint_en;
//wire	o_lspro_fetched;
//wire	memwb_rst_i;
//assign	memwb_rst_i = memwb_rst | reset;

ysyx_210195_MEMWB_reg	ysyx_210195_MEMWB_REG(
	.clk(clock),
	.reset(reset),
	.handshake_done(i_if_fetched),
	.memwb_rst(memwb_rst),
	.memwb_ena(1'b1),
//from if
	.i_ifififif_pc_out(o_ififif_pc_out),
//	.i_ifififif_fetched(o_ififif_fetched),
//	.i_ifififif_time_intr_r(o_ififif_time_intr_r),
//	.i_ifififif_addr(o_ififif_addr),
	
//from id
//	.i_ididid_rs1_r_ena(o_idid_rs1_r_ena),				//--csr_reg,regfile
//	.i_ididid_rs1_r_addr(o_idid_rs1_r_addr),	//--csr_reg,regfile
//	.i_ididid_rs2_r_ena(o_idid_rs2_r_ena),				//--regfile
//	.i_ididid_rs2_r_addr(o_idid_rs2_r_addr),	//--regfile
	.i_ididid_rd_w_ena(o_idid_rd_w_ena),				//--csr_reg,regfile
	.i_ididid_rd_w_addr(o_idid_rd_w_addr),		//--csr_reg,regfile
	.i_ididid_op2(o_idid_op2),	//rge
//from ctrlid
	.i_ctrlidctrlidctrlid_wb_sel(o_ctrlidctrlid_wb_sel),			//regfile
	.i_ctrlidctrlidctrlid_ecall_en(o_ctrlidctrlid_ecall_en),					//wb
	.i_ctrlidctrlidctrlid_mret_en(o_ctrlidctrlid_mret_en),					//wb
//from exe
	.i_exeexe_data(o_exe_data),		//--WB
//from CSR_UNIT
	.i_csrunitcsrunit_csr_addr(o_csrunit_csr_addr),		//wb
	.i_csrunitcsrunit_csr_w_ena(o_csrunit_csr_w_ena),			//wb
	.i_csrunitcsrunit_csr_w_data(o_csrunit_csr_w_data),		//wb
	.i_csrunitcsrunit_csr_r_ena(o_csrunit_csr_r_ena),			//wb
	.i_csrunitcsrunit_csr_r_data(o_csrunit_csr_r_data),	
//from ctrlexe
	.i_ctrlexectrlexe_load_axi_en(o_ctrlexe_load_axi_en),			//regfile
	.i_ctrlexectrlexe_load_clint_en(o_ctrlexe_load_clint_en),		//regfile
	.i_ctrlexectrlexe_store_clint_en(o_ctrlexe_store_clint_en),

//from	ls_pro
	.i_lspro_axi_ld_data(i_lspro_axi_ld_data),
//	.i_lspro_fetched(i_lspro_fetched),
	
	.i_clintclint_load_data(o_clint_load_data),

	.o_ifififif_pc_out(o_ifififif_pc_out),
//	.o_ifififif_fetched(o_ifififif_fetched),
//	.o_ifififif_time_intr_r(o_ifififif_time_intr_r),
//	.o_ifififif_addr(o_ifififif_addr),

//	.o_ididid_rs1_r_ena(o_ididid_rs1_r_ena),				//--csr_reg,regfile
//	.o_ididid_rs1_r_addr(o_ididid_rs1_r_addr),	//--csr_reg,regfile
//	.o_ididid_rs2_r_ena(o_ididid_rs2_r_ena),				//--regfile
//	.o_ididid_rs2_r_addr(o_ididid_rs2_r_addr),	//--regfile
	.o_ididid_rd_w_ena(o_ididid_rd_w_ena),				//--csr_reg,regfile
	.o_ididid_rd_w_addr(o_ididid_rd_w_addr),		//--csr_reg,regfile
	.o_ididid_op2(o_ididid_op2),	
	
	.o_ctrlidctrlidctrlid_wb_sel(o_ctrlidctrlidctrlid_wb_sel),			//regfile
	.o_ctrlidctrlidctrlid_ecall_en(o_ctrlidctrlidctrlid_ecall_en),					//wb
	.o_ctrlidctrlidctrlid_mret_en(o_ctrlidctrlidctrlid_mret_en),					//wb
	
	.o_exeexe_data(o_exeexe_data),		//--WB
	
	.o_csrunitcsrunit_csr_addr(o_csrunitcsrunit_csr_addr),		//wb
	.o_csrunitcsrunit_csr_w_ena(o_csrunitcsrunit_csr_w_ena),			//wb
	.o_csrunitcsrunit_csr_w_data(o_csrunitcsrunit_csr_w_data),		//wb
	.o_csrunitcsrunit_csr_r_ena(o_csrunitcsrunit_csr_r_ena),			//wb
	.o_csrunitcsrunit_csr_r_data(o_csrunitcsrunit_csr_r_data),
	
	.o_ctrlexectrlexe_load_axi_en(o_ctrlexectrlexe_load_axi_en),			//regfile
	.o_ctrlexectrlexe_load_clint_en(o_ctrlexectrlexe_load_clint_en),		//regfile
	.o_ctrlexectrlexe_store_clint_en(o_ctrlexectrlexe_store_clint_en),
	
	.o_lspro_axi_ld_data(o_lspro_axi_ld_data),
//	.o_lspro_fetched(o_lspro_fetched),
	.o_clintclint_load_data(o_clintclint_load_data)

);
reg		w_ctrl;
always @(posedge clock)	begin
	if(reset)
		w_ctrl <= 1'b0;
	else
		w_ctrl <= i_if_fetched;
		
end
wire	ecall_w_en;
assign	ecall_w_en = o_ctrlidctrlidctrlid_ecall_en & (w_ctrl & (~time_intr_r));
wire	mret_w_en;
assign	mret_w_en = o_ctrlidctrlidctrlid_mret_en & (w_ctrl & (~time_intr_r));
wire	csr_write_ena;
assign	csr_write_ena = (w_ctrl & (~time_intr_r)) & o_csrunitcsrunit_csr_w_ena;

//wire	csr_reg_r_ena;
//assign	csr_reg_r_ena = o_csrunitcsrunit_csr_r_ena | i_csrunit_csr_r_ena;
wire	[63:0]	csr_mepc_pc;
assign	csr_mepc_pc = (o_ififif_pc_out != 0) ? o_ififif_pc_out :
						(o_ifif_pc_out != 0) ? o_ifif_pc_out :
						(o_if_pc_out != 0) ? o_if_pc_out : i_if_pc_out;
//o_ctrlidctrlidctrlid_mret_en ? o_ifif_pc_out : o_ififif_pc_out;
ysyx_210195_csr_reg	ysyx_210195_CSR_REG(
		.clk(clock),
		.rst(reset),
		//csr_unit -> csr_reg
		.csr_addr(o_csrunitcsrunit_csr_addr),				//csr索引地址
		.csr_w_ena(csr_write_ena),
		.csr_r_ena(o_csrunitcsrunit_csr_r_ena),
		.csr_w_data(o_csrunitcsrunit_csr_w_data),
		
		.csr_r_ena_unit(i_csrunit_csr_r_ena),
		.csr_addr_unit(i_csrunit_csr_addr),
		
		.ecall_w_en(ecall_w_en),
		.mret_w_en(mret_w_en),
		.pc(o_ifififif_pc_out),
		
		.if_addr(csr_mepc_pc),
		
		.time_overstep(time_overstep),
		.time_intr_r(time_intr_r),
		
		.csr_r_data(csr_r_data),
		.csr_r_data_unit(csr_r_data_unit),
		
		.mtvec_o(mtvec_r),
		.mepc_o(mepc_r),
		.MTIP_o(MTIP)
		);

//wire [`REG_DATA_LEN-1:0] regs [0:31];

wire	w_ena;
/*
assign	w_ena = o_ctrlexectrlexe_load_axi_en ? 
		(o_ididid_rd_w_ena & o_lspro_fetched & (~o_ifififif_time_intr_r)) : 
		(o_ididid_rd_w_ena & i_if_fetched & (~o_ifififif_time_intr_r));
*/

assign	w_ena = o_ididid_rd_w_ena & w_ctrl & (~time_intr_r);
ysyx_210195_regfile	ysyx_210195_REG(
    .clk(clock),
	.rst(reset),
	
	.w_addr(o_ididid_rd_w_addr),
	.exe_data(o_exeexe_data),
	.csr_r_data(o_csrunitcsrunit_csr_r_data),
	.csr_r_ena(o_csrunitcsrunit_csr_r_ena),
//	.mem_ld_data(mem_ld_data),
	.load_axi_data(o_lspro_axi_ld_data),
	.load_clint_data(o_clintclint_load_data),
	.load_axi_en(o_ctrlexectrlexe_load_axi_en),
	.load_clint_en(o_ctrlexectrlexe_load_clint_en),	

	.pc(o_ifififif_pc_out),
	.wb_sel(o_ctrlidctrlidctrlid_wb_sel),			//10:load_mem,01:pc+4,else exe_data
	.w_ena(w_ena),
	
	.r_addr1(i_id_rs1_r_addr),
	.r_data1(rs1_data),
	.r_ena1(i_id_rs1_r_ena),
	
	.r_addr2(i_id_rs2_r_addr),
	.r_data2(rs2_data),
	.r_ena2(i_id_rs2_r_ena)
//	.regs_o(regs)
    );
assign	load_store_addr = o_exeexe_data;
assign	store_clint_data = o_ididid_op2;
assign	clint_w_ena = o_ctrlexectrlexe_store_clint_en & 
						w_ctrl & 
						(~time_intr_r);	
assign	load_clint_en = o_ctrlexectrlexe_load_clint_en;

	
/*	
axi_arbi	AXI_ARBI(
//if request
	.if_valid_i(if_valid),
	.if_ready_o(if_ready),				//->if_stage
	.if_req_i(if_req),
	.if_data_o(inst_data_read),
	.if_addr_i(if_addr),
	.if_size_i(if_size),
	.if_resp_o(if_resp),

//data request
	.ls_valid_i(ls_valid_o),
	.ls_ready_o(ls_ready_i),
	.ls_req_i(ls_req_o),
	.load_data_o(load_data_i),
	.ls_addr_i(exe_data),			//exe_data
//	input	[1:0]	store_data_i,		//op2
	.ls_size_i(ls_size_o),
	.ls_resp_o(ls_resp),
	
//to axi_rw
	.rw_valid_o(rw_valid_o),
	.rw_ready_i(rw_ready_i),
	.rw_req_o(rw_req_o),
	.data_read_i(data_read_i),
//	output	[63:0]	data_write_o,		//op2
	.rw_addr_o(rw_addr_o),
	.rw_size_o(rw_size_o),
	.rw_resp_i(rw_resp_i)
	);
*/
//assign	data_write_o = op2;
//wire	[63:0]	data_write_0;
//master0 write addr
wire	aw_ready_0;
wire	aw_valid_0;
wire	[AXI_ADDR_WIDTH-1:0] aw_addr_0;
wire	[AXI_ID_WIDTH-1:0]	aw_id_0;		//write address channel ID
wire	[AXI_USER_WIDTH-1:0] aw_user_0;		//自定义
wire	[2:0]	aw_prot_0;				//access permissions
wire	[7:0]	aw_len_0;			//burst lenth = aw_len + 1
wire	[2:0]	aw_size_0;			//本次burst中，一次transferde的字节数
wire	[1:0]	aw_burst_0;			//burst_type
wire			aw_lock_0;
wire	[3:0]	aw_cache_0;			//memory types
wire	[3:0]	aw_qos_0;			//Quality of service identifier for a write transaction
wire	[3:0]	aw_region_0;		//多接口时用
		
		//master0 write data
wire	w_ready_0;
wire	w_valid_0;
wire	[AXI_DATA_WIDTH-1:0]	w_data_0;
wire	[7:0]	w_strb_0;				//标志有效位
wire	w_last_0;					//标志最后一次传输
wire	[AXI_USER_WIDTH-1:0]	w_user_0;
		
		//write response master0
wire	b_ready_0;
wire	b_valid_0;
wire	[1:0]	b_resp_0;
wire	[AXI_ID_WIDTH-1:0]	b_id_0;
wire	[AXI_USER_WIDTH-1:0]	b_user_0;
		
		//read address channel master0
wire	ar_ready_0;
wire	ar_valid_0;
wire	[AXI_ADDR_WIDTH-1:0]	ar_addr_0;
wire	[2:0]	ar_prot_0;
wire	[AXI_ID_WIDTH-1:0]	ar_id_0;			//read address channel identifier
wire	[AXI_USER_WIDTH-1:0]	ar_user_0;
wire	[7:0]	ar_len_0;
wire	[2:0]	ar_size_0;
wire	[1:0]	ar_burst_0;
wire			ar_lock_0;
wire	[3:0]	ar_cache_0;
wire	[3:0]	ar_qos_0;
wire	[3:0]	ar_region_0;
		
		//read data channel master0
wire	r_ready_0;
wire	r_valid_0;
wire	[1:0]	r_resp_0;
wire	[AXI_DATA_WIDTH-1:0]	r_data_0;
wire	r_last_0;
wire	[AXI_ID_WIDTH-1:0]	r_id_0;
wire	[AXI_USER_WIDTH-1:0]	r_user_0;
//master 0
ysyx_210195_axi_rw ysyx_210195_AXI0(
		//glabal
		.clock(clock),
		.reset(reset),					//high work
		
		//user input/output
		.rw_valid_i(if_valid),
		.rw_ready_o(if_ready),
		.rw_req_i(if_req),				//require read/write
		.data_read_o(inst_data_read),
		.data_write_i(64'd0),
		.rw_addr_i(i_if_addr),
		.rw_size_i(if_size),			//传输的字节数
		.rw_resp_o(if_resp),
		
		//MASTER write addr
		.aw_ready_i(aw_ready_0),			//slave -> master,ready to receive write address
		.aw_valid_o(aw_valid_0),			//master -> slave,write address valid
		.aw_addr_o(aw_addr_0),		//write sddress
		.aw_id_o(aw_id_0),			//write address channel ID
		.aw_user_o(aw_user_0),		//自定义
		.aw_prot_o(aw_prot_0),				//access permissions
		.aw_len_o(aw_len_0),			//burst lenth = aw_len + 1
		.aw_size_o(aw_size_0),			//本次burst中，一次transferde的字节数
		.aw_burst_o(aw_burst_0),			//burst_type
		.aw_lock_o(aw_lock_0),
		.aw_cache_o(aw_cache_0),			//memory types
		.aw_qos_o(aw_qos_0),			//Quality of service identifier for a write transaction
		.aw_region_o(aw_region_0),		//多接口时用
		
		//master write data
		.w_ready_i(w_ready_0),
		.w_valid_o(w_valid_0),
		.w_data_o(w_data_0),
		.w_strb_o(w_strb_0),				//标志有效位
		.w_last_o(w_last_0),						//标志最后一次传输
		.w_user_o(w_user_0),
		
		//write response
		.b_ready_o(b_ready_0),
		.b_valid_i(b_valid_0),
		.b_resp_i(b_resp_0),
		.b_id_i(b_id_0),
		.b_user_i(b_user_0),
		
		//read address channel
		.ar_ready_i(ar_ready_0),
		.ar_valid_o(ar_valid_0),
		.ar_addr_o(ar_addr_0),
		.ar_prot_o(ar_prot_0),
		.ar_id_o(ar_id_0),			//read address channel identifier
		.ar_user_o(ar_user_0),
		.ar_len_o(ar_len_0),
		.ar_size_o(ar_size_0),
		.ar_burst_o(ar_burst_0),
		.ar_lock_o(ar_lock_0),
		.ar_cache_o(ar_cache_0),
		.ar_qos_o(ar_qos_0),
		.ar_region_o(ar_region_0),
		
		//read data channel
		.r_ready_o(r_ready_0),
		.r_valid_i(r_valid_0),
		.r_resp_i(r_resp_0),
		.r_data_i(r_data_0),
		.r_last_i(r_last_0),
		.r_id_i(r_id_0),
		.r_user_i(r_user_0)	
		
	);
	
	
//master1 write addr
wire	aw_ready_1;
wire	aw_valid_1;
wire	[AXI_ADDR_WIDTH-1:0] aw_addr_1;
wire	[AXI_ID_WIDTH-1:0]	aw_id_1;			//write address channel ID
wire	[AXI_USER_WIDTH-1:0] aw_user_1;	//自定义
wire	[2:0]	aw_prot_1;				//access permissions
wire	[7:0]	aw_len_1;			//burst lenth = aw_len + 1
wire	[2:0]	aw_size_1;			//本次burst中，一次transferde的字节数
wire	[1:0]	aw_burst_1;			//burst_type
wire			aw_lock_1;
wire	[3:0]	aw_cache_1;			//memory types
wire	[3:0]	aw_qos_1;			//Quality of service identifier for a write transaction
wire	[3:0]	aw_region_1;		//多接口时用
		
		//master1 write data
wire	w_ready_1;
wire	w_valid_1;
wire	[AXI_DATA_WIDTH-1:0]	w_data_1;
wire	[7:0]	w_strb_1;				//标志有效位
wire	w_last_1;						//标志最后一次传输
wire	[AXI_USER_WIDTH-1:0]	w_user_1;
		
		//write response master1
wire	b_ready_1;
wire	b_valid_1;
wire	[1:0]	b_resp_1;
wire	[AXI_ID_WIDTH-1:0]	b_id_1;
wire	[AXI_USER_WIDTH-1:0]	b_user_1;
		
		//read address channel master1
wire	ar_ready_1;
wire	ar_valid_1;
wire	[AXI_ADDR_WIDTH-1:0]	ar_addr_1;
wire	[2:0]	ar_prot_1;
wire	[AXI_ID_WIDTH-1:0]	ar_id_1;			//read address channel identifier
wire	[AXI_USER_WIDTH-1:0]	ar_user_1;
wire	[7:0]	ar_len_1;
wire	[2:0]	ar_size_1;
wire	[1:0]	ar_burst_1;
wire			ar_lock_1;
wire	[3:0]	ar_cache_1;
wire	[3:0]	ar_qos_1;
wire	[3:0]	ar_region_1;
		
		//read data channel master1
wire	r_ready_1;
wire	r_valid_1;
wire	[1:0]	r_resp_1;
wire	[AXI_DATA_WIDTH-1:0]	r_data_1;
wire	r_last_1;
wire	[AXI_ID_WIDTH-1:0]	r_id_1;
wire	[AXI_USER_WIDTH-1:0]	r_user_1;

wire	[63:0]	data_write_o;
assign	data_write_o = o_idid_op2;
//master 1
ysyx_210195_axi_rw ysyx_210195_AXI1(
		//glabal
		.clock(clock),
		.reset(reset),					//high work
		
		//user input/output
		.rw_valid_i(ls_valid_o),
		.rw_ready_o(ls_ready_i),
		.rw_req_i(ls_req_o),				//require read/write
		.data_read_o(load_data_i),
		.data_write_i(data_write_o),
		.rw_addr_i(o_exe_data),
		.rw_size_i(ls_size_o),			//传输的字节数
		.rw_resp_o(ls_resp),
		
		//MASTER write addr
		.aw_ready_i(aw_ready_1),			//slave -> master,ready to receive write address
		.aw_valid_o(aw_valid_1),			//master -> slave,write address valid
		.aw_addr_o(aw_addr_1),		//write sddress
		.aw_id_o(aw_id_1),			//write address channel ID
		.aw_user_o(aw_user_1),		//自定义
		.aw_prot_o(aw_prot_1),				//access permissions
		.aw_len_o(aw_len_1),			//burst lenth = aw_len + 1
		.aw_size_o(aw_size_1),			//本次burst中，一次transferde的字节数
		.aw_burst_o(aw_burst_1),			//burst_type
		.aw_lock_o(aw_lock_1),
		.aw_cache_o(aw_cache_1),			//memory types
		.aw_qos_o(aw_qos_1),			//Quality of service identifier for a write transaction
		.aw_region_o(aw_region_1),		//多接口时用
		
		//master write data
		.w_ready_i(w_ready_1),
		.w_valid_o(w_valid_1),
		.w_data_o(w_data_1),
		.w_strb_o(w_strb_1),				//标志有效位
		.w_last_o(w_last_1),						//标志最后一次传输
		.w_user_o(w_user_1),
		
		//write response
		.b_ready_o(b_ready_1),
		.b_valid_i(b_valid_1),
		.b_resp_i(b_resp_1),
		.b_id_i(b_id_1),
		.b_user_i(b_user_1),
		
		//read address channel
		.ar_ready_i(ar_ready_1),
		.ar_valid_o(ar_valid_1),
		.ar_addr_o(ar_addr_1),
		.ar_prot_o(ar_prot_1),
		.ar_id_o(ar_id_1),			//read address channel identifier
		.ar_user_o(ar_user_1),
		.ar_len_o(ar_len_1),
		.ar_size_o(ar_size_1),
		.ar_burst_o(ar_burst_1),
		.ar_lock_o(ar_lock_1),
		.ar_cache_o(ar_cache_1),
		.ar_qos_o(ar_qos_1),
		.ar_region_o(ar_region_1),
		
		//read data channel
		.r_ready_o(r_ready_1),
		.r_valid_i(r_valid_1),
		.r_resp_i(r_resp_1),
		.r_data_i(r_data_1),
		.r_last_i(r_last_1),
		.r_id_i(r_id_1),
		.r_user_i(r_user_1)	
		
	);
	
	
ysyx_210195_axi_interconnect ysyx_210195_INTERCONNECT(
//from 	master0:	instruction fetched	
		//master0 write addr
		.clock(clock),
		.reset(reset),
		
		.aw_ready_0(aw_ready_0),
		.aw_valid_0(aw_valid_0),
		.aw_addr_0(aw_addr_0),
		.aw_id_0(aw_id_0),			//write address channel ID
		.aw_user_0(aw_user_0),		//自定义
		.aw_prot_0(aw_prot_0),				//access permissions
		.aw_len_0(aw_len_0),			//burst lenth = aw_len + 1
		.aw_size_0(aw_size_0),			//本次burst中，一次transferde的字节数
		.aw_burst_0(aw_burst_0),			//burst_type
		.aw_lock_0(aw_lock_0),
		.aw_cache_0(aw_cache_0),			//memory types
		.aw_qos_0(aw_qos_0),			//Quality of service identifier for a write transaction
		.aw_region_0(aw_region_0),		//多接口时用
		
		//master0 write data
		.w_ready_0(w_ready_0),
		.w_valid_0(w_valid_0),
		.w_data_0(w_data_0),
		.w_strb_0(w_strb_0),				//标志有效位
		.w_last_0(w_last_0),						//标志最后一次传输
		.w_user_0(w_user_0),
		
		//write response master0
		.b_ready_0(b_ready_0),
		.b_valid_0(b_valid_0),
		.b_resp_0(b_resp_0),
		.b_id_0(b_id_0),
		.b_user_0(b_user_0),
		
		//read address channel master0
		.ar_ready_0(ar_ready_0),
		.ar_valid_0(ar_valid_0),
		.ar_addr_0(ar_addr_0),
		.ar_prot_0(ar_prot_0),
		.ar_id_0(ar_id_0),			//read address channel identifier
		.ar_user_0(ar_user_0),
		.ar_len_0(ar_len_0),
		.ar_size_0(ar_size_0),
		.ar_burst_0(ar_burst_0),
		.ar_lock_0(ar_lock_0),
		.ar_cache_0(ar_cache_0),
		.ar_qos_0(ar_qos_0),
		.ar_region_0(ar_region_0),
		
		//read data channel master0
		.r_ready_0(r_ready_0),
		.r_valid_0(r_valid_0),
		.r_resp_0(r_resp_0),
		.r_data_0(r_data_0),
		.r_last_0(r_last_0),
		.r_id_0(r_id_0),
		.r_user_0(r_user_0),

//from master1: read/write data		
		//master1 write addr
		.aw_ready_1(aw_ready_1),
		.aw_valid_1(aw_valid_1),
		.aw_addr_1(aw_addr_1),
		.aw_id_1(aw_id_1),			//write address channel ID
		.aw_user_1(aw_user_1),		//自定义
		.aw_prot_1(aw_prot_1),				//access permissions
		.aw_len_1(aw_len_1),			//burst lenth = aw_len + 1
		.aw_size_1(aw_size_1),			//本次burst中，一次transferde的字节数
		.aw_burst_1(aw_burst_1),			//burst_type
		.aw_lock_1(aw_lock_1),
		.aw_cache_1(aw_cache_1),			//memory types
		.aw_qos_1(aw_qos_1),			//Quality of service identifier for a write transaction
		.aw_region_1(aw_region_1),		//多接口时用
		
		//master1 write data
		.w_ready_1(w_ready_1),
		.w_valid_1(w_valid_1),
		.w_data_1(w_data_1),
		.w_strb_1(w_strb_1),				//标志有效位
		.w_last_1(w_last_1),						//标志最后一次传输
		.w_user_1(w_user_1),
		
		//write response master1
		.b_ready_1(b_ready_1),
		.b_valid_1(b_valid_1),
		.b_resp_1(b_resp_1),
		.b_id_1(b_id_1),
		.b_user_1(b_user_1),
		
		//read address channel master1
		.ar_ready_1(ar_ready_1),
		.ar_valid_1(ar_valid_1),
		.ar_addr_1(ar_addr_1),
		.ar_prot_1(ar_prot_1),
		.ar_id_1(ar_id_1),			//read address channel identifier
		.ar_user_1(ar_user_1),
		.ar_len_1(ar_len_1),
		.ar_size_1(ar_size_1),
		.ar_burst_1(ar_burst_1),
		.ar_lock_1(ar_lock_1),
		.ar_cache_1(ar_cache_1),
		.ar_qos_1(ar_qos_1),
		.ar_region_1(ar_region_1),
		
		//read data channel master1
		.r_ready_1(r_ready_1),
		.r_valid_1(r_valid_1),
		.r_resp_1(r_resp_1),
		.r_data_1(r_data_1),
		.r_last_1(r_last_1),
		.r_id_1(r_id_1),
		.r_user_1(r_user_1),		


//to slave
		//MASTER write addr
		.aw_ready_i(aw_ready_i),			//slave -> master,ready to receive write address
		.aw_valid_o(aw_valid_o),			//master -> slave,write address valid
		.aw_addr_o(aw_addr_o),		//write sddress
		.aw_id_o(aw_id_o),			//write address channel ID
		.aw_user_o(aw_user_o),		//自定义
		.aw_prot_o(aw_prot_o),				//access permissions
		.aw_len_o(aw_len_o),			//burst lenth = aw_len + 1
		.aw_size_o(aw_size_o),			//本次burst中，一次transferde的字节数
		.aw_burst_o(aw_burst_o),			//burst_type
		.aw_lock_o(aw_lock_o),
		.aw_cache_o(aw_cache_o),			//memory types
		.aw_qos_o(aw_qos_o),			//Quality of service identifier for a write transaction
		.aw_region_o(aw_region_o),		//多接口时用
		
		//master write data
		.w_ready_i(w_ready_i),
		.w_valid_o(w_valid_o),
		.w_data_o(w_data_o),
		.w_strb_o(w_strb_o),				//标志有效位
		.w_last_o(w_last_o),						//标志最后一次传输
		.w_user_o(w_user_o),
		
		//write response
		.b_ready_o(b_ready_o),
		.b_valid_i(b_valid_i),
		.b_resp_i(b_resp_i),
		.b_id_i(b_id_i),
		.b_user_i(b_user_i),
		
		//read address channel
		.ar_ready_i(ar_ready_i),
		.ar_valid_o(ar_valid_o),
		.ar_addr_o(ar_addr_o),
		.ar_prot_o(ar_prot_o),
		.ar_id_o(ar_id_o),			//read address channel identifier
		.ar_user_o(ar_user_o),
		.ar_len_o(ar_len_o),
		.ar_size_o(ar_size_o),
		.ar_burst_o(ar_burst_o),
		.ar_lock_o(ar_lock_o),
		.ar_cache_o(ar_cache_o),
		.ar_qos_o(ar_qos_o),
		.ar_region_o(ar_region_o),
		
		//read data channel
		.r_ready_o(r_ready_o),
		.r_valid_i(r_valid_i),
		.r_resp_i(r_resp_i),
		.r_data_i(r_data_i),
		.r_last_i(r_last_i),
		.r_id_i(r_id_i),
		.r_user_i(r_user_i)

);	

reg	[7:0]	o_ididid_inst_opcode;
always @(posedge handshake_done)	begin
	if(reset)
		o_ididid_inst_opcode <= 8'd0;
	else
		o_ididid_inst_opcode <= o_idid_inst_opcode;
end
	
wire	inst_mcycle;
assign	inst_mcycle = ((o_csrunitcsrunit_csr_addr == 12'hb00) && (o_ididid_inst_opcode[4:0] == 5'b11100)) ? 1'b1 : 1'b0;
//自定义putch：0x0b//////////////////////////////
wire	inst_myself;
assign	inst_myself = (o_ididid_inst_opcode == 8'b000_11110) ? 1'b1 : 1'b0;
//reg		inst_myself_r;
//always @(posedge clock)
//  begin
//	 inst_myself_r <= inst_myself; 
//  end
always @(posedge inst_myself)
  begin
	if(o_ididid_inst_opcode == 8'b000_11110)
		$write("%c",ysyx_210195_REG.regs[10]);
  end	
//////////////////////////////////////////////////


///////////////////////////////////////////////////////////////////////////////////////////// 
//需要skip的指令

wire	skip;
reg		skip_r;
assign	skip = inst_myself | inst_mcycle 
				| o_ctrlexectrlexe_load_clint_en | o_ctrlexectrlexe_store_clint_en;

always @(posedge clock)
  begin
		skip_r <= skip;
  end

///////////////////////////////////////////////////////////////////////////////////////////////

// Difftest
reg cmt_wen;
reg [7:0] cmt_wdest;
reg [`REG_DATA_LEN-1:0] cmt_wdata;
reg [`REG_DATA_LEN-1:0] cmt_pc;
reg [31:0] cmt_inst;
reg cmt_valid;
reg trap;
reg [7:0] trap_code;
reg [63:0] cycleCnt;
reg [63:0] instrCnt;
reg [`REG_DATA_LEN-1:0] regs_diff [0 : 31];

wire inst_valid = if_ready & (i_if_addr > 64'h0000_0000_8000_000c);

wire cmt_valid_t;
/*assign	cmt_valid_t = (i_if_addr > 64'h0000_0000_8000_000c) ? 
		(o_ctrlexectrlexe_load_axi_en ? 
		(o_lspro_fetched & (~o_ifififif_time_intr_r)) : 
		(i_if_fetched & (~o_ifififif_time_intr_r))) :
		1'b0;*/
//assign	cmt_valid_t = (i_if_addr > 64'h0000_0000_8000_000c) ? 
//					(i_if_fetched & (~o_ifififif_time_intr_r)) : 1'b0
reg	o_if_time_intr_r;
reg	o_ifif_time_intr_r;
reg	o_ififif_time_intr_r;
reg	o_ifififif_time_intr_r;
always @(posedge handshake_done)	begin
	o_if_time_intr_r <= time_intr_r;
	o_ifif_time_intr_r <= o_if_time_intr_r;
	o_ififif_time_intr_r <= o_ifif_time_intr_r;
	o_ifififif_time_intr_r <= o_ififif_time_intr_r;
end
assign	cmt_valid_t = w_ctrl & (~o_ifififif_time_intr_r);

		
reg  [31:0]	o_ifif_inst;
reg  [31:0]	o_ififif_inst;
reg  [31:0]	o_ifififif_inst;
always @(posedge handshake_done)	begin
	if(reset)	begin
		o_ifif_inst <= 32'd0;
		o_ififif_inst <= 32'd0;
		o_ifififif_inst <= 32'd0;
	end
	else	begin
		o_ifif_inst <= o_if_inst;
		o_ififif_inst <= o_ifif_inst;
		o_ifififif_inst <= o_ififif_inst;	
	
	end
end

always @(posedge clock) begin
  if (reset) begin
    {cmt_wen, cmt_wdest, cmt_wdata, cmt_pc, cmt_inst,cmt_valid , trap, trap_code, cycleCnt, instrCnt} <= 0;
  end

  else if (~trap) begin
    cmt_wen <= w_ena;
    cmt_wdest <= {3'd0, o_ididid_rd_w_addr};
    cmt_wdata <= ysyx_210195_REG.w_data;
    cmt_pc <= o_ifififif_pc_out;
    cmt_inst <= o_ifififif_inst;
    cmt_valid <= (o_ifififif_pc_out == 64'd0) ? 1'b0 : 
				((o_ifififif_inst == 32'h0000_0013) && 
				(o_ifififif_pc_out == 64'h0000_0000_8000_0000)) ? 
				1'b0 : cmt_valid_t;

 //   regs_diff <= regs;

    trap <= o_ifififif_inst[6:0] == 7'h6b;
 //   trap_code <= regs[10][7:0];
    cycleCnt <= cycleCnt + 1;
    instrCnt <= instrCnt + inst_valid;
  end
end

reg cmt_valid_r;
reg cmt_wen_r;
reg [`REG_DATA_LEN-1:0] cmt_wdata_r;
always @(posedge clock)		begin
	cmt_valid_r <= cmt_valid;
	cmt_wen_r <= cmt_wen;
	cmt_wdata_r <= cmt_wdata;
end

DifftestInstrCommit DIFFINSTCOMMIT(
  .clock    ( clock ),
  .coreid   ( 8'd0 ),//8bit
  .index    ( 8'd0 ),//8bit
  .valid    ( cmt_valid_r),
  .pc       ( o_ifififif_pc_out ),//64bit
  .instr    ( cmt_inst ),//32bit
  .skip     ( skip_r ),
  .isRVC    ( 1'b0 ),
  .scFailed ( 1'b0 ),
  .wen      ( cmt_wen_r ),
  .wdest    ( cmt_wdest ),//8bit
  .wdata    ( cmt_wdata_r ) //64bit
);

reg 	time_intr_r_r;
always @(posedge clock)
	time_intr_r_r <= time_intr_r;

wire	[31:0] intr_cause;
wire	[31:0] intr_num;
assign	intr_cause = (time_intr_r & (~time_intr_r_r)) ? 32'd7 : 32'd0;
assign	intr_num = (time_intr_r & (~time_intr_r_r)) ? 32'd7 : 32'd0;
reg		[31:0] intr_cause_r;
reg		[31:0] intr_num_r;
always @(posedge clock)	begin
	intr_cause_r <= intr_cause;
	intr_num_r <= intr_num;

end

DifftestArchEvent	DIFFTESTARCHEVENT(
	.clock(clock),
	.coreid(8'd0),
	.intrNO(intr_num_r),
	.cause(intr_cause_r),			//计时器中断
	.exceptionPC(csr_mepc_pc),
	.exceptionInst(32'd0)
);
	
	
DifftestTrapEvent DifftestTrapEvent(
  .clock              (clock),
  .coreid             (0),
  .valid              (trap),
  .code               (ysyx_210195_REG.regs[10][7:0]),
  .pc                 (cmt_pc),
  .cycleCnt           (ysyx_210195_CSR_REG.mcycle),
  .instrCnt           (instrCnt)
);

DifftestArchIntRegState DifftestArchIntRegState (
  .clock              (clock),
  .coreid             (0),
  .gpr_0              (ysyx_210195_REG.regs[0]),
  .gpr_1              (ysyx_210195_REG.regs[1]),
  .gpr_2              (ysyx_210195_REG.regs[2]),
  .gpr_3              (ysyx_210195_REG.regs[3]),
  .gpr_4              (ysyx_210195_REG.regs[4]),
  .gpr_5              (ysyx_210195_REG.regs[5]),
  .gpr_6              (ysyx_210195_REG.regs[6]),
  .gpr_7              (ysyx_210195_REG.regs[7]),
  .gpr_8              (ysyx_210195_REG.regs[8]),
  .gpr_9              (ysyx_210195_REG.regs[9]),
  .gpr_10             (ysyx_210195_REG.regs[10]),
  .gpr_11             (ysyx_210195_REG.regs[11]),
  .gpr_12             (ysyx_210195_REG.regs[12]),
  .gpr_13             (ysyx_210195_REG.regs[13]),
  .gpr_14             (ysyx_210195_REG.regs[14]),
  .gpr_15             (ysyx_210195_REG.regs[15]),
  .gpr_16             (ysyx_210195_REG.regs[16]),
  .gpr_17             (ysyx_210195_REG.regs[17]),
  .gpr_18             (ysyx_210195_REG.regs[18]),
  .gpr_19             (ysyx_210195_REG.regs[19]),
  .gpr_20             (ysyx_210195_REG.regs[20]),
  .gpr_21             (ysyx_210195_REG.regs[21]),
  .gpr_22             (ysyx_210195_REG.regs[22]),
  .gpr_23             (ysyx_210195_REG.regs[23]),
  .gpr_24             (ysyx_210195_REG.regs[24]),
  .gpr_25             (ysyx_210195_REG.regs[25]),
  .gpr_26             (ysyx_210195_REG.regs[26]),
  .gpr_27             (ysyx_210195_REG.regs[27]),
  .gpr_28             (ysyx_210195_REG.regs[28]),
  .gpr_29             (ysyx_210195_REG.regs[29]),
  .gpr_30             (ysyx_210195_REG.regs[30]),
  .gpr_31             (ysyx_210195_REG.regs[31])
);

/*
DifftestArchIntRegState DifftestArchIntRegState (
  .clock              (clock),
  .coreid             (0),
  .gpr_0              (regs_diff[0]),
  .gpr_1              (regs_diff[1]),
  .gpr_2              (regs_diff[2]),
  .gpr_3              (regs_diff[3]),
  .gpr_4              (regs_diff[4]),
  .gpr_5              (regs_diff[5]),
  .gpr_6              (regs_diff[6]),
  .gpr_7              (regs_diff[7]),
  .gpr_8              (regs_diff[8]),
  .gpr_9              (regs_diff[9]),
  .gpr_10             (regs_diff[10]),
  .gpr_11             (regs_diff[11]),
  .gpr_12             (regs_diff[12]),
  .gpr_13             (regs_diff[13]),
  .gpr_14             (regs_diff[14]),
  .gpr_15             (regs_diff[15]),
  .gpr_16             (regs_diff[16]),
  .gpr_17             (regs_diff[17]),
  .gpr_18             (regs_diff[18]),
  .gpr_19             (regs_diff[19]),
  .gpr_20             (regs_diff[20]),
  .gpr_21             (regs_diff[21]),
  .gpr_22             (regs_diff[22]),
  .gpr_23             (regs_diff[23]),
  .gpr_24             (regs_diff[24]),
  .gpr_25             (regs_diff[25]),
  .gpr_26             (regs_diff[26]),
  .gpr_27             (regs_diff[27]),
  .gpr_28             (regs_diff[28]),
  .gpr_29             (regs_diff[29]),
  .gpr_30             (regs_diff[30]),
  .gpr_31             (regs_diff[31])
);
*/
wire	[63:0]	sstatus;
assign	sstatus = ysyx_210195_CSR_REG.mstatus & 64'h8000_0003_000D_E122;

DifftestCSRState DifftestCSRState(
  .clock              (clock),
  .coreid             (0),
  .priviledgeMode     (3),
  .mstatus            (ysyx_210195_CSR_REG.mstatus),
  .sstatus            (sstatus),
  .mepc               (ysyx_210195_CSR_REG.mepc),
  .sepc               (0),
  .mtval              (0),
  .stval              (0),
  .mtvec              (ysyx_210195_CSR_REG.mtvec),
  .stvec              (0),
  .mcause             (ysyx_210195_CSR_REG.mcause),
  .scause             (0),
  .satp               (0),
  .mip                (0),
  .mie                (ysyx_210195_CSR_REG.mie),
  .mscratch           (ysyx_210195_CSR_REG.mscratch),
  .sscratch           (0),
  .mideleg            (0),
  .medeleg            (0)
);

DifftestArchFpRegState DifftestArchFpRegState(
  .clock              (clock),
  .coreid             (0),
  .fpr_0              (0),
  .fpr_1              (0),
  .fpr_2              (0),
  .fpr_3              (0),
  .fpr_4              (0),
  .fpr_5              (0),
  .fpr_6              (0),
  .fpr_7              (0),
  .fpr_8              (0),
  .fpr_9              (0),
  .fpr_10             (0),
  .fpr_11             (0),
  .fpr_12             (0),
  .fpr_13             (0),
  .fpr_14             (0),
  .fpr_15             (0),
  .fpr_16             (0),
  .fpr_17             (0),
  .fpr_18             (0),
  .fpr_19             (0),
  .fpr_20             (0),
  .fpr_21             (0),
  .fpr_22             (0),
  .fpr_23             (0),
  .fpr_24             (0),
  .fpr_25             (0),
  .fpr_26             (0),
  .fpr_27             (0),
  .fpr_28             (0),
  .fpr_29             (0),
  .fpr_30             (0),
  .fpr_31             (0)
);



endmodule	
		
		
		